Dynamic Random-Access-Memory (DRAM) devices are usually sold to a consumer in the form of a Single In-Line Memory Module (SIMM). On a given SIMM printed circuit board, there are usually several DRAMs, and such DRAMs are usually accessed simultaneously providing, for example, a byte or word's worth of binary data.
DRAMs are sometimes manufactured with a failing memory location. It is desirable not to throw away DRAMs with failing memory locations because this results in a loss of revenue. Instead, DRAMs with failing memory locations can still be incorporated onto a SIMM while still maintaining proper SIMM functionality.
To by-pass the failing memory locations, another type of chip, typically an application specific integrated circuit (ASIC), can be included on the SIMM and programmed to reroute the address of the failing location away from the failing memory location to another source of back-up memory which exists on the SIMM. Such back-up memory can be located in the ASIC itself, or could constitute a designated portion of DRAM memory already included on the SIMM. Either way, the failing locations, by the use of the programmable ASIC, are effectively masked from the SIMM consumer, who notices no loss in functionality. U.S. Pat. No. 5,315,552 (Yoneda) describes a basic use of this technique.
DRAMs used in SIMM manufacturing can be tested individually both before and after assembly onto a SIMM printed circuit board. It is usually the case that the individual DRAMs can be scrutinized for failures with greater sensitivity before assembly of the DRAMs onto the SIMM. This results because SIMM testers are generally not as sophisticated as individual chip testers, and because the electrical interference of the SIMM board and the other DRAMs present on the SIMM board, preclude an unhampered investigation of a single DRAM once it is assembled onto a SIMM. For this reason, it is desirable to use the data gathered while testing the DRAMs before SIMM assembly to assist in programming the ASIC to mask the failing locations.
Before SIMM assembly, DRAMs may be tested under a variety of conditions to try and aggravate potentially latent failures. For example, a DRAM could be tested at cold (-10 Centigrade) or high (+85 Centigrade) temperatures, or subject to various timing conditions, or subject to different voltage conditions, etc.
When testing a DRAM in each of these different ways, a "fail map" of the device can be generated. A "fail map" is constructed by writing a pre-selected pattern into a DRAM, and then reading out the pattern. If the DRAM is working properly, then the pattern written into the DRAM and the pattern read out of the DRAM, when compared, should be the same. If there are no differences, the fail map will be blank. But if a difference exists between the two patterns, for example, if a "1" is written into a particular memory location, but a "0" is read, or vice versa, then the device has a failure at the given memory location. The failing memory location (or locations) is logged into the fail map. Typically, the fail maps for a given device are stored by means of a computer which is connected to the memory tester which generated the fail map.
Testing the device under various conditions is desirable because some modes of failure may be present only when subjected to a particular test condition (e.g., a given memory location may only fail at high temperature, or when subjected to lower than usual voltages, etc.). Thus, by testing a DRAM before SIMM assembly under several different conditions, several different fail maps can be generated, which may or may not be equivalent. From these fail maps, a "worst case fail map" can be generated which contains all failing locations (generated from any of the test conditions) in a single map.
In the prior art, the programming of the ASIC to mask out failing memory locations is inefficient. Typically, after assembly of the DRAMs on the SIMM, the SIMM itself is tested to determine if there are any failing memory locations. If failing locations are detected, the fail maps of the DRAMs which were generated before SIMM assembly are searched to see if a "match" can be located. In other words, the fail maps of an individual DRAM are read off of the SIMM and are compared to the hosts of files that were collected from the individual DRAMs pre-SIMM assembly. Typically, this process of matching compares the SIMM data to the worst case fail map generated before SIMM assembly. This is done because, as previously mentioned, the individual DRAM fail maps are generally much more sensitive and therefore provide the most conservative summary of which failing locations should be masked off to maximize product reliability. In other words, the pre-assembly data may be relied on, instead of the SIMM data, when programming the ASIC.
However, the matching process can be both time consuming and inaccurate. It is time consuming because the pattern matching process must sort through relatively large fail maps to try and locate a matching map. Also, it is inaccurate since the fails generated when the DRAMs are on a SIMM will likely only show a portion of the failures that were highlighted in the DRAM fail maps generated before SIMM assembly, therefore making pattern matching difficult.